[sv-bc] Mantis 1348: 10.8,9 don't say that statement labels create named blocks

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue Feb 21 2006 - 08:15:54 PST
Hi,

Following the email discussion, I filed Mantis 1348 on the subject of statement labels:

This comes from the email discussions beginning at http://www.eda.org/sv-bc/hm/3905.html.

10.8 has the following example:

labelB: fork // label before the begin or fork ...
join : labelB
  
The block_identifier labelB after 'join' is not clear. This is a block_identifier whereas the labelB before the 'fork' is a statement label, not a block identifier.

10.8 does not justify how you can do this. 10.8 does not say that "label: statement" is the same as "begin :label statement end".

10.9 has the following example, 

module ...
always always1: begin ... t1: task1( ); ... end 
...
endmodule

always begin
...
disable u1.always1.t1; // exit task1, which was called from always1 (static) 
end

(Here also the IEEE reformatting caused "(static)" to jump to the next line.)

Here the statement label 'always1' here is used as a hierarchical scope, where 10.8 does not say that labels create such scopes.

I found that
17.2 ("Immediate assertions") says, "The optional statement label (identifier and colon) creates a named block around the assertion statement (or any other SystemVerilog statement) and can be displayed using the %m format specification."

Such a statement certainly belongs in 10.8 and also in the discussion of hierarchies in Clause 19.

But it is still a problem. The wording implies that

labelB: fork
        join

is equivalent to 

begin :labelB
  fork
  join
end

and not to 

fork :labelB
join

And even if it were, it still does not say that you can use a statement label in place of a block identifier after an end or join.

Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6852
+972 54 721-1033
I don't represent Intel 
Received on Tue Feb 21 08:16:03 2006

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