RE: [sv-bc] 10.8 Named blocks and statement labels - question

From: Jonathan Bromley <jonathan.bromley_at_.....>
Date: Thu Feb 16 2006 - 01:26:30 PST
Steven Sharp wrote:

> I don't really see much use for statement labels anyway.

As far as I'm aware, it's the only way to get a name on
a concurrent assertion.  Properties have names, but 
assertions don't.  Presumably that's why the definition
is tucked away in 17.2 (so that I embarrassed myself by
not noticing it!).
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                   Email: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves 
all rights of privilege in  respect thereof. It is intended for the use of 
the addressee only. If you are not the intended recipient please delete it 
from  your  system, any  use, disclosure, or copying  of this  document is 
unauthorised. The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.
Received on Thu Feb 16 01:26:39 2006

This archive was generated by hypermail 2.1.8 : Thu Feb 16 2006 - 01:30:16 PST