RE: [sv-bc] Question on ?: with "any" data type

Gordon,

Section 8.18 states:
SystemVerilog extends the conditional operator to non integral types and
aggregate expressions using the following
rules:
- If both first expression and second expression are of integral type, the
operation proceeds as defined.
- If first expression or second expression is an integral type and the
opposing expression can be implicitly cast
to an integral type, the cast is made and proceeds as defined.
- For all other cases, the type of first expression and second expression
must be equivalent. 

If cond_predicate evaluates to an ambiguous value, then both first
expression and second expression shall be
evaluated and their results shall be combined, element-by-element. If the
elements match, the element is
returned. If they do not match, then the default-uninitialized value for
that element's type shall be returned.
Francoise
    '

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Gordon
Vreugdenhil
Sent: Tuesday, February 07, 2006 11:42 AM
To: SV_BC List
Subject: [sv-bc] Question on ?: with "any" data type

The SV LRM claims the ?: is defined for "any" data type.  Is the following
supposed to be legal?  If so, what is the value of z?

    module top;
       integer x[1] = '{ 1 };
       integer y[1] = '{ 2 };
       integer z[5];
       reg cond;

       initial z = cond ? x : y;
    endmodule

In 1364, when "cond" has the value 'x, the result is defined bitwise by
Table 5-20.  But bitwise operations aren't defined for unpacked types (and
would be quite bad for class handles or similar).  I see 3 choices:
     1) ?: should be restricted to integral types
     2) it must be a sim time error if the condition is 'x for
        a non-integral result
     3) the condition must be restricted to a 2-state value if
        the result is a non-integral type.

I think I'd prefer (3) since that allows "natural" expression of assignments
for class handles, etc. while ensuring that we can check legality at elab
time.

Gord.
--
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com