[sv-bc] Clocking blocks - discrepancies hard to resolve

hi,

I've already made myself a nuisance about clocking 
blocks, and I'm going to do it again.  Sorry.

I attach an example of clocking blocks and programs that
I believe is sound, but behaves spectacularly differently
in the two simulators to which I have access.  Worse still,
it is beyond my comprehension skills to infer from the 
LRM text which if either of them is correct.

The attached rather simple code example attempts to
follow the spirit of the use of clocking and program.
The program uses ##1 cycle delays throughout; it 
accesses the design through a clocking block with 
non-zero skews; the design is zero-delay RTL.

If I am abusing the constructs in some way in this
example, I would be pleased to know - but I put it
to you that if so, I'm probably not the only user
who will make such errors.  If, as I believe, the
example is sound, could someone kindly show me how
to infer its correct behaviour from the LRM so that
I can decide which vendor(s) should receive a bug
report?

Here are the discrepant results:

    Vendor A                  Vendor B
~~~~~~~~~~~~~~~~~~       ~~~~~~~~~~~~~~~~~~~
...                       ...
(clock cycle 2)           (clock cycle 2)
   cb.Q     = x              cb.Q     = x
   in_s.D,Q = x,x            in_s.D,Q = 0,x
   in_z.D,Q = x,x            in_z.D,Q = 0,0
(clock cycle 3)           (clock cycle 3)
   cb.Q     = x              cb.Q     = 0
   in_s.D,Q = 0,0            in_s.D,Q = 0,0
   in_z.D,Q = 0,0            in_z.D,Q = 0,0
(clock cycle 4)           (clock cycle 4)
   cb.Q     = 0              cb.Q     = 0
   in_s.D,Q = 0,0            in_s.D,Q = 0,0
   in_z.D,Q = 0,0            in_z.D,Q = 0,0
(clock cycle 5)           (clock cycle 5)
   cb.Q     = 0              cb.Q     = 0
   in_s.D,Q = 0,0            in_s.D,Q = 1,0
   in_z.D,Q = 0,0            in_z.D,Q = 1,1
(clock cycle 6)           (clock cycle 6)
   cb.Q     = 0              cb.Q     = 1
   in_s.D,Q = 1,1            in_s.D,Q = 1,1
   in_z.D,Q = 1,1            in_z.D,Q = 1,1
(clock cycle 7)           (clock cycle 7)
   cb.Q     = 1              cb.Q     = 1
   in_s.D,Q = 1,1            in_s.D,Q = 1,1
   in_z.D,Q = 1,1            in_z.D,Q = 1,1
...                       ...

And here's the source code:

// test5b  Jonathan Bromley, 7 Feb 2006
//
// simple example of clocking block that *should* be race-free,
// but gives different behaviour in two different simulators

// __________________________________________________ DUT ___
//
module test5b_dut(input bit clk, input logic D, output logic Q);
  always @(posedge clk) Q <= D;
endmodule

// ____________________________________________ TESTBENCH ___
//
program p5b (output logic D, input logic Q, input bit clk);

  // Three clocking blocks: the first is testbench drive and
  // receive, the way I would like to do it; the others are
  // there to illustrate some monitoring behaviour
  //
  default clocking cb @(posedge clk);
    output #7 D; input #1 Q;
  endclocking

  clocking in_s @(posedge clk);
    input #1step D; input #1step Q;
  endclocking

  clocking in_z @(posedge clk);
    input #0 D; input #0 Q;
  endclocking

  // Cycle-based procedural testbench code.  Note that
  // the test activity is entirely controlled by ##1
  // delays, equivalent to @cb.
  //
  initial begin : TestMyFF
    for (int i=0; i<10; i=i+1) ##1 begin
      cb.D <= (i>2? 1: 0);
      $display("(clock cycle %0d)", ($time+5)/10);
      $display("   cb.Q     = %b",    cb.Q          );
      $display("   in_s.D,Q = %b,%b", in_s.D, in_s.Q);
      $display("   in_z.D,Q = %b,%b", in_z.D, in_z.Q);
    end
    $stop;
  end

endprogram

// _______________________________ TOP LEVEL AND CLOCK GENERATOR ___
//
module test5b;
  logic D, Q;
  bit   clk;
  test5b_dut DUT(.*);
  p5b        tester(.*);
  always #5 clk = ~clk;
endmodule
-- 
Jonathan Bromley, Consultant

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