Re: [sv-bc] Opinion on merging of P1364 and P1800

-----Non-member submission from Ben Cohen-----
From: vhdlcohen@aol.com
Sent: Saturday, January 28, 2006 10:05 PM
To: sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org
Subject: Re: [sv-ec] Re: [sv-bc] Opinion on merging of P1364 and P1800

I actually ran into someone form a large corporation who thought that 
Verilog is not a subset of SystemVerilog,
 and was ambivalent about transitioning to SV.
 Ben


 -----Original Message-----
 From: Alec Stanculescu <alec@fintronic.com>
 To: Brad.Pierce@synopsys.com
 Cc: sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org
 Sent: Sat, 28 Jan 2006 20:27:04 -0800
 Subject: Re: [sv-ec] Re: [sv-bc] Opinion on merging of P1364 and P1800

 Brad,

 I agree with your arguments and share your opinion that there are not
 enough resources to mearge the two LRMs.

 However, the main reason for mearging the LRMs is to ensure that
 Verilog becomes a subset of SystemVerilog. Since this seems to
 everybody such a big task, it follows that Verilog is not a subset of
 SystemVerilog.

 A second reason for mearging the LRMs is the fact that the P1800
 "promised" to produce one LRM at the next release of the language and
 provided a specific date. Of course, the committee is allowed to change
 its mind, but usually it is preferable to keep promises.

 Regards,

 Alec