Re: [sv-ec] Re: [sv-bc] Opinion on merging of P1364 and P1800

Brad, 

I agree with your arguments and share your opinion that there are not
enough resources to mearge the two LRMs.

However, the main reason for mearging the LRMs is to ensure that
Verilog becomes a subset of SystemVerilog. Since this seems to
everybody such a big task, it follows that Verilog is not a subset of
SystemVerilog.

A second reason for mearging the LRMs is the fact that the P1800
"promised" to produce one LRM at the next release of the language and
provided a specific date. Of course, the committee is allowed to change
its mind, but usually it is preferable to keep promises.

Regards,

Alec