>From: "Michael (Mac) McNamara" <mcnamara@cadence.com> >the simulator must pick if possible the order of evaluating f(a), f(b) and f(c) in such a way that only one function evaluation returns true. Wow! This is hard, and I would argue not really what I would want my simulator to be doing; nor is it something I imagine a synthesis tool could create logic to replicate in hardware; nor would I want to use up area in silicon for such logic! Which is exactly why the LRM does not specify that. The simulator can pick any order of evaluation it likes. If it happens to find one that does not violate the requirement, then it is allowed to not produce a warning. If it finds one that does violate it, then it produces a warning. The wording of the description is obscure, but what it means is something quite practical. Steven Sharp sharp@cadence.comReceived on Thu Jan 12 16:51:25 2006
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