Re: [sv-bc] Selects use self-determined evaluation, but does it say so in LRM?

P1364 refers to these as "integer expressions", which
hints at other interpretations.  The range expressions used
to declare vectors and arrays are similarly (under)specified.

One thing /not/ specified is any relationship between the
types used to declare the range of a given dimension and the
type of the expressions used to index across that dimension.
I think we can assume that there /is/ no such relationship,
even though the compiler internally constructs expressions that
bring these together.   In practice, notice that implementations
probably ALL use native (e.g. 32 bit signed) integer arithmetic
to compute the final offsets from the base address of the vector.

The only guidance P1364 offers on the subject of expression bit
width is that it should be "natural" to the situation.  The nearest
sorts of examples are the right operand of a shift operator and
the repeat count of a repeat concatenation.  Both of these are
explicitly said to be self-determined, even though they are
similarly treated as "integer expressions" in the LRM text.  So
I think your interpretation is correct - occasional existing behavior
to the contrary notwithstanding.

Greg Jaxon

Brad Pierce wrote:
> I don’t find in the LRM that in v[E1], v[E2:E3], v[E4+:E5], and 
> v[E6-:E7] the expressions E1,..,E7 are evaluated in their 
> self-determined contexts.  For example,
> 
>  
> 
> module test(test_bit); // should be 1
> 
> output test_bit;
> 
>  
> 
>   wire [-4:3] w = 3'b111;
> 
>  
> 
>   `define M 2'b01 << 2 >> 2
> 
>   wire [2:0]              t   =   `M ;
> 
>   assign test_bit = w[t] != w[`M];
> 
>  
> 
> endmodule
> 
>  
> 
> -- Brad
> 
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>                          v
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