[sv-bc] event regions

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Thu Dec 29 2005 - 06:43:35 PST
There is some unclearness in Section 9.

First, it seems that the Preponed and Postponed regions are both PLI and non-PLI regions, is this correct? 

If so, Figure 9-1 confuses this by showing each region as either PLI or implicitly non-PLI.

Also, #1step is described in 9.3, "Conceptually, this #1step sampling is identical to taking the data samples in the Preponed region of the current time slot." 

However, in 15.2, it says, "A 1step input skew allows input signals to sample their steady-state values in the time step immediately before the clock event (i.e., in the preceding Postponed region)", and in 15.12, "If the input skew is not an explicit #0, then the value sampled corresponds to the signal value at the Postponed region of the time step skew time units prior to the clocking event (see Figure 15-1 in 15.3)."

This is confusing.

Thanks,
Shalom

Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6852
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I don't represent Intel 
Received on Thu Dec 29 06:43:47 2005

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