Re: [sv-ac] RE: [sv-bc] Differences between 1800 and 3.1a

From: Brad Pierce <Brad.Pierce_at_.....>
Date: Tue Dec 20 2005 - 09:03:38 PST
The most complete, context-rich history of differences is the closed
issues in the Mantis DB.  Every change has a formal proposal in the
Attached Files field.  Use guest/guest in http://eda.org/svdb .

 

Also, please note that all of the changes of IEEE Std. 1364-2005, such
as encryption, uwire, and the generate enhancements are implicit changes
of the P1800 standard.

 

-- Brad

 

________________________________

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Eduard Cerny
Sent: Tuesday, December 20, 2005 5:57 AM
To: Michael Smith; Bresticker, Shalom; sv-bc@eda.org; sv-ac@eda.org;
sv-ec@eda.org
Subject: RE: [sv-ac] RE: [sv-bc] Differences between 1800 and 3.1a

 

I believe that there exists a version of the P1800 document where the
differences are color coded.

 

ed

 

	 

	
________________________________


	From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf
Of Michael Smith
	Sent: Tuesday, December 20, 2005 4:05 AM
	To: Bresticker, Shalom; sv-bc@eda.org; sv-ac@eda.org;
sv-ec@eda.org
	Subject: [sv-ac] RE: [sv-bc] Differences between 1800 and 3.1a

	As much as possible! Ideally versions of the IEEE LRMs with
change bars. Failing that, a comprehensive list of "significant" 

	differences from a user's point of view. (I am updating Doulos's
Systemverilog Golden Reference Guide.) Obviously I can go through the
documents myself, but if someone's already done the work, it would be a
great help.

	 

	Thanks,

	Mike

		-----Original Message-----
		From: Bresticker, Shalom
[mailto:shalom.bresticker@intel.com]
		Sent: 20 December 2005 08:54
		To: Michael Smith; sv-bc@eda.org; sv-ac@eda.org;
sv-ec@eda.org
		Subject: RE: [sv-bc] Differences between 1800 and 3.1a

		How much detail do you want?

		 

		Shalom

		 

		
________________________________


		From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]
On Behalf Of Michael Smith
		Sent: Tuesday, December 20, 2005 10:41 AM
		To: sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org
		Subject: [sv-bc] Differences between 1800 and 3.1a

		 

		Is there anywhere a list of the differences between
IEEE-1800 SystemVerilog and 3.1a?

		And between Verilog-2005 and Verilog-2001?

		 

		Thanks,

		Michael Smith,

		Doulos Ltd.

		 
Received on Tue Dec 20 09:03:59 2005

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