Date: Thu Dec 08 2005 - 00:55:21 PST
Mark, That is an inappropriate way of looking at it. The variable is not used to model a three-state ("tri-state" is a trademark, I believe) bus, but rather a three-state driver. There is a difference if the bus has more than one driver. It is really no different from combinational logic description using a variable, which sometimes drives 0 and sometimes 1. Here it also sometimes drives high-impedance, i.e., does not drive. Typically, it is used in one of two ways. In one way, there is a three-stated wire which is a common output of several modules. From the point of view of each module, it is an output only, which is sometimes driven and sometimes not. Since it is output only, a variable can be used. The second way is by continuous assignments from the variable drivers to a common wire. Since port connections from a variable to a wire are also equivalent to a continuous assignment, the two ways are essentially the same. This is a very common way to describe three-state drivers. We may use a variable in an always block because the logic may be complex and easier to describe using behavioral statements like if and case, which we cannot use in continuous assignments. In fact, your own company's manual on Verilog for synthesis shows several examples using reg's, including an example of a registered three-state driver, where both the three-state enable and the data are outputs of flip-flops. Shalom ________________________________ From: Mark Hartoog [mailto:Mark.Hartoog@synopsys.com] Sent: Monday, December 05, 2005 7:01 PM To: Bresticker, Shalom; sv-bc@eda.org Subject: RE: [sv-bc] @* vs. always_comb I really don't think that variables are the appropriate way of modeling tri-state busses. Wires are much better for this. You wouldn't use a unresolved wire to model a tri-state bus, why try to use a variable?
