RE: [sv-bc] A genvar is not a "constant" -- 6.1 Note

I don't think the difference is important in this context.

 

Shalom

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Wednesday, December 07, 2005 5:44 PM
To: sv-bc@eda.org
Subject: [sv-bc] A genvar is not a "constant" -- 6.1 Note

 

According to the Note of 6.1, "Verilog constants are literals,
genvars[,] parameters, localparams, and specparams."

 

But, in fact, a genvar is not a constant.  What is a constant is the
implicit localparam associated with the genvar and its loop generate
construct.

 

According to 12.4.1 in the 1364 standard  -

 

"Within the generate block of a loop generate construct, there is an
implicit localparam declaration. This is an integer parameter that has
the same name and type as the loop index variable, and its value within
each instance of the generate block is the value of the index variable
at the time the instance was elaborated. This parameter can be used
anywhere within the generate block that a normal parameter with an
integer value can be used. It can be referenced with a hierarchical
name.

 

"Because this implicit localparam has the same name as the genvar, any
reference to this name inside the loop generate block will be a
reference to the localparam, not to the genvar. As a consequence, it is
not possible to have two nested loop generate constructs that use the
same genvar."

 

 

-- Brad