[sv-bc] Re BTF 419:Reconsider for 1364-2005 proposals made for 1364-2001

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue Nov 22 2005 - 05:09:07 PST
This is the detailed discussion from BTF priorities sub-group about BTF
419.
 
Shalom
 
________________________________


Priorities sub-group minutes 2004-06-21


From: Shalom.Bresticker@freescale.com
<mailto:Shalom.Bresticker@freescale.com?Subject=Re:%20Priorities%20sub-g
roup%20minutes%202004-06-21> 
Date: Mon Jun 28 2004 - 06:55:21 PDT 

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________________________________

The Priorities sub-group of the BTF met last Monday, 2004-06-21 
(maybe for the last time...) 


We started with issue 419, 
"Reconsider for 1364-2005 proposals made for 1364-2001" 


At this point, we moved to the table of BTF Enhancement Requests for 
1364-2001 and looked at those which were not accepted and implemented at

that time: 


B10 - Behavioral assignment to wire 
        This wanted the ability to do a procedural assignment to an 
        inout port wire. Even Cliff Cummings opposed this at the time. 
        Note that these are very often multiply-driven signals. 
        We decided not to reconsider this. 


B12 - Continuous assignment case expressions 
        This wanted the ability to write something like 
    assign data_out = case(mux_select) 
                        2'h0: mux_1; 
                        2'h1: mux_2; 
                        2'h2: mux_3; 
                        2'h3: mux_4; 
                       endcase 


        We agreed to bring this up again. 
        It is nice and probably not hard to implement, 
        but does not add new functionality, so we gave it 
        priority MEDIUM 


B15 - Built-in sizeof(x) function 
         
        To get the size of a vector or structure. 
        Should be useable in constant expressions. 
        Like $bits in SystemVerilog. 
        Priority MEDIUM now, HIGH after definition of complex datatypes 


B16 - Access to last specified bit 


        Like $left and $right in SystemVerilog. 
        Should be done together with B15. 


B17 - Separate compilation capability 


        Already submitted 


B18 - Enumerated types 
         
        Already submitted 


B20 - Pullup/pulldown optional X-drive time 


        "pullup/down models be modified to accept an optional time
(hence 
backwards compatible) and to have them drive an x for that time before 
driving the final pulled state." 


        After discussion, we concluded that this proposal is not 
        consistent with Verilog, and is doable in a different way, 
        so we did not recommend it for further. 


B21 - Automatic init of integers to 0 


        Not back-compatible and doable manually. 
        We do not recommend this for further work. 


At this point, we discussed a new idea of compiler directives for 
initialization of variables to 0 or 1 or random. Some tools do this
today 
by a command-line switch. Both methods have advantages and
disadvantages. 
An advantage of compiler directives is that they can be selective, i.e.,

on part of the design. A disadvantage is that it involves touching the 
design files. We recommend this for further consideration with 
priority MEDIUM. 


B25 - Structs 


        Already submitted 


B28 - Bottom testing loop 


        In SystemVerilog. 
        Yes, but MEDIUM-LOW priority. 


B31 - Allowing parameters to define the length of a constant. 


        Shalom: This would be useful. 
        Steven: There could be order dependencies, since parameter
values 
        are only determined at elaboration time. Need restrictions. 
        If we did this as a conversion function instead of as part of
the 
        syntax for specifying a constant, it would be better. 
        Shalom: OK 
        MEDIUM-HIGH priority. 


B32 - Non-Blocking events 


        Want to trigger events with a delay in a non-blocking manner. 
        Done in SystemVerilog as ->> operator. 
        MEDIUM. 


B40 - Trig functions 
         
        Already submitted 


Here we finished the old list and moved back to the new list. 


421 - Move 17.9.3 ($dist code) to Annex. 


        Yes. LOW. 


422 - Extend $dumpvars to exclude a signal or module 


        Yes, we discussed various additional ways of extending $dumpvars

        as already implemented in various tools, currently and in the
past. 
        A good idea, but need more detailed proposals. 
        MEDIUM-HIGH after being fleshed out. 


427 - Combine 4.1.3 and 4.1.6 


        A good idea, but need someone to do it, and it needs to be done 
        carefully. Better to not do it than to do it wrong. 
        MEDIUM. 


We will not meet Monday, July 5, Steven will be on vacation. 
We will meet July 19, assuming the working group still exists by then
and still has something to do... 


-- 
Shalom Bresticker                         Shalom.Bresticker
@freescale.com
Design & Reuse Methodology                            Tel: +972 9
9522268
Freescale Semiconductor Israel, Ltd.                  Fax: +972 9
9522890
POB 2208, Herzlia 46120, ISRAEL                      Cell: +972 50
5441478
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