Hi Johny, Can someone please upload the drafts that were submitted to RevCom onto the IEEE 1800 site? The latest files there are P1364-D8_preliminary1.pdf 13-Jul-2005 23:04 3.6M P1800-D6_preliminary1.pdf 13-Jul-2005 23:11 3.8M Thanks, Dave ________________________________ From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Johny Srouji Sent: Wednesday, August 24, 2005 7:19 AM To: Michael Smith Cc: owner-sv-ac@eda.org; sv-ac@eda.org; sv-bc@eda.org; sv-ec@eda.org; Karen.Pieper@synopsys.com Subject: [sv-bc] Re: [sv-ac] Long list of LRM errata Regarding the status of the ballot: "P1800 Draft 8 was submitted to RevCom on 8/10 and it will be reviewed by RevCom on 9/21 and then by the IEEE standards on 9/22". Therefore, during this period the LRM is frozen and no changes can be made until it is reviewed and approved by the standards committee. P1800 WG will meet after that date and decide on the next steps and plans regarding SystemVerilog. As for issue that come up at this stage, I suggest reporting them so that we get them filed in our data base for future work. Regards, --- Johny. "Michael Smith" <michael.smith@doulos.com> Sent by: owner-sv-ac@eda.org 08/24/2005 06:01 AM To <sv-ac@eda.org>, <sv-bc@eda.org>, <sv-ec@eda.org> cc Subject [sv-ac] Long list of LRM errata I have a list of errata that I have been gathering. How are the vendors resloving the ambiguities and omissions that they are finding? Will we end up with a separate SV language for each vendor? What is the status of the IEEE ballot? Can corrections still be made? When is SystemVerilog now expected to become a standard? Thanks, Mike Smith SystemVerilog P1800 Draft 5 Prelim 1 Manual =========================================== Pages are printed (PDF) P211 (223) half way down "ended" and "matched" should be courier. P212 (224) remove space between arrayA and [16] P214 (226) "More complex sequential behaviors are described by SystemVerilog sequences" The previous paragraph has already talked about this. Maybe the para breaks are in the wrong places. P216 (228) "The clocking_event ..." this is not mentioned in the preceding syntax table. This sentence is out of place and makes the text confusing to read. It should perhaps go soon after syntax 18-2 or with the first example on P217 (229). P222 (234) 3rd para from end: $sampled should use courier font (twice) P224 (236) As noted on reflector, what if the type of expression1 is two-valued? As noted on reflector, what if there wan't such an clocking event? S/b same as too many ticks back. P235 (247) Declarations of properties are out of place here - this is "sequences"; "properties" come later. Section 18.11.5 It is not clear what "the property will hold on any extension of the path" means. E.g. what is a "path"? What is the "extension" of a path? (These terms are defined in the PSL LRM) P240 (252) list_of_formals still appears in syntax, even though properties now use tf_port_list (and in ANnex A). Is direction allowed? P356 (368) Why do $rose, $fell etc. not appear in Syntax 24-8? - How does one bind into a top-level instance (e.g. $root.top)? If you put a bind outside any modules, it goes into a compilation unit package. What would cause it to be elaborated? You could create a second top-level module, bindings, to include the "top level" bind commands. [Emailed to Johny Srouji, 26/5/05] SystemVerilog P1800 Draft 5 Prelim 5 Manual =========================================== P118 (130) The third ampersand in the syntax for cond_predicate should be coloured red. P133 (147) Final blocks execute when $finish is called, whether implicitly or explicitly. Does this mean that if a design includes no program instances, then final blocks are not executed if the simulation ends simply due to there being no more events? ($finish is not called in this case.) Is this the intent? P141 (155) 2nd para. Why does this talk about "formal arguments passed by reference"? In the following example, is "automatic int m = j" illustrating this? If yes, how? If not, the text is unclear. P143 (157) Syntax the enum in of class process is incorrect: Should be typedef enum {...} state; P144 (158) k is declared but not used. Should the line of the example that calls process::self be "begin job[k] = process::self(); ... ; end? P199 (213) peek. The final sentence "Calling the peek() method .." doesn't seem to make sense. How can calling peek cause a process to be unblocked? Here is my analysis: peek or get only blocks if the mailbox is empty. Unblocking requires a put or try_put. This will only unblock one process that is blocked by get, but MAY unblock other processes IF they have been blocked by peek. Is there a race? or do the put and get always see the same message? P202 (216) The BNF for wait_order is either wrong, or implies that e1.triggered is a hierarchical identifier. The latter is not clear from Appendix A. P210 (224) clocking_decl_assignment ::= signal_identifier [=expression]. In the BNF, "signal_identifer" is a simple_identifier, not an hierarchical_identifier. But the interface examples have signals in the form interface_identifier.member P210 (224) clocking cd2 references b.cmd, which is not allowed, because cmd is not in the modport test of bus_B. P214 (228) Syntax 15-4 has the intra-assignment form of clocking_drive first and the blocking form second. The words on P215 (229) assume the opposite order. P215 (229) The first of the Examples has the comment "drive data in the NBA region of the current cycle" What is the current cycle at the start of simulation? For example, given clocking cb @(posedge clk); output In; Is "initial In <= 1;" the same as "initial In <= ##1 1;?" What about "initial ##0 In <= 1;" and "initial In <= ##0 1;"? P215 (229) Conflicting bits - does Z cause a conflict or not? Or are the rules the same as for multiple drivers for a wire or tri net, or for ambiguous conditions when using the conditional operator (?:)? P219 (223) Are a program's ports program variables or not? (ModelSim 6.1 thinks so, VCS X-2005.06-Beta2-5 thinks not). The example on p345 (359) seems to suggest that program ports are not program variables. P285 (299) A bind directive may be included in a compilation unit scope. Does it have any effect? Under what circumstances? P358 (372) Is the reference to "i.True" in module sub valid? The text of 20.9 is unclear - are objects other than those legal to be listed in modports accessible by port reference? P396 (410) "DPI" is deprecated, yet examples in the text use "DPI", not "DPI-C". P542 (556) Should event.triggered appear somewhere as an expression? Or it covered by "hierarchical_identifier select"? Putting it another way, where e is an event, is "e.triggered" an expression? P551 (565) Syntax the enum in of class process is incorrect: Should be typedef enum {...} state; P594 (608) "DPI" gives compile time error, yet standard seems to permit its use. Compile time errors usually mean the code fails to compile and in particular cannot be simulated. What does "positive" mean in the LRM? There are conflicting examples and the term is not defined. Examples: p198 (212) return value of try_put - "positive" is used to mean "not 0 or negative". p206 (220) The delay_control must evaluate to a positive integer value; later it is clear that #0 is allowed. SystemVerilog P1800 Draft 6 Prelim 1 Manual =========================================== P33 (35) Class Packet has incomplete declarations of new and send. Either declare them extern, or complete the declaration. P51 (63) Should a queue initializer have a preceding '? If so, the LRM is wrong, if not, the term "array literal" should not be used. P51 (63) The sentence "like arrays, queues can be manipulated using the indexing, concatenation, slicing operator syntax, and equality operators" implies that concatenation may be used with unpacked arrays. The semantics are not defined anywhere. I would expect them on p.39 (51) P58 (70) Section 6.3, Constants. "Verilog provides three constructs for defining elaboration-time constants: parameter, localparam and specparam." There follows examples of localparam, specparam and const. What's "const"? P76 (88) Which operators are/are not allowed for object variables? == != >> <<. Are there any others? What about ===. P106 (118) int j = { "A", "B", "C", "D", "E" }; - should this have a preceding '? GENERAL POINT - when must array literals (assignment patterns) be used? P200 (212) This implies that "signals" are program (or module) ports or hierarchical references. However, Section 15.4 permits arbitrary hierarchical expressions. P208 (220) 15.14.1 says "Synchronous signal drives are processed as nonblocking assignments". Does that then mean that in a program, clocking signals cannot be program varaibles, which require blocking assignments)? P347 (359) Syntax for virtual interface requires "interface_identifier", which is a straightforward identifier. Example (p350 (362) shows identifer.modport_name. The semantics of this are not described. P350 (362) Last line - should this be "assert property (b1.sb.p1);" ? -- Michael Smith Senior Consultant DOULOS - Developing Design Know-how VHDL * SystemC * Verilog * SystemVerilog * e * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: michael.smith@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Received on Thu Aug 25 08:43:47 2005
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