Re: [sv-bc] Is an unnamed block with declarations a scope?

>From: Greg Jaxon <Greg.Jaxon@synopsys.com>
>
>Mac used a task invocation to bring up an additional issue:
>Implicit wires must choose some scope to govern their lifetimes.
>
>I cringe to suggest it, but implicit wires could belong to
>the module, or wherever they would otherwise land if there
>were no unnamed scopes.

This is not a problem.  In Verilog, there is no way to declare
a wire in a procedural block, either explicitly or implicitly.
The constructs that create implicit wires (which do NOT include
task calls), can only occur at the module level or in a generate
construct.

1364-2005 already makes clear that an implicit wire resulting
from a reference inside a generate construct will be declared in
the scope created by that generate construct.  This is true whether
the scope has a name, or is unnamed.

At any rate, implicit wires are not an issue for these unnamed
procedural blocks.

Steven Sharp
sharp@cadence.com