Re: [sv-ec] RE: [sv-bc] Is this a valid syntax

>This is old syntax that was removed in SV3.1a. You are probably using a
>simulator that is not up to date.

Or one whose implementors decided this was an obvious extension that
should be allowed.  I don't see any problem with this syntax assuming
a base type of logic, as happens in similar declarations elsewhere in
Verilog.

Steven Sharp
sharp@cadence.com