[sv-bc] expression width calculation

Hi Guys,

We had an issue here regarding the right semantic for:

		wire a;
		assign a = 4'b0101 == (signed' (3'b101));
		
Does 'a' equal 1 or 0?

Can you please comment on our interpretation and make it clearer.

The question that we ask is in fact: does the width-extension of the
constant happen before the signed-cast was applied or after. The
standard is not clear enough on the topics related to calculation of
expression widths. 

Base on Yulik's observations, we tend to use the following reasoning
(which is not 100% clear) in this case:
 
*         According to Verilog's 5.5.2 "Steps for evaluating an
expression", one should first determine expression type (size and sign)
and then propagate it down to context-determined operands.
*         The propagation stops when it reaches a "simple" operand (a
"primary" in BNF). A cast is a simple operand, according to the
definition of "primary" in SV BNF. Since the cast is a simple operand,
we need to convert the type and size of the cast expression itself, not
its operand. 
*         After propagation stops, the operand is converted to the
propagated type and size. If the operand is extended, it is
sign-extended only if the propagated type is signed. 
*         The cast expression has an "initial" size of 3 and it is
signed (to my understanding). Now we need to convert it to the
propagated type. The question is what is the propagated type?
*         According to the 5.5.2 section, equality operands are neither
fully self-determined nor fully context-determined. Their operands
should affect each other as if they were context-determined operands
with a result type and size determined from them. The size is chosen as
the maximum of the two operand sizes, so the resulting size is 4.
However, nothing special is said how the signing should be chosen in
operands of equality operators.
*         According to 5.5.1, for non-self-determined operands (and the
operands of equality operators are not self-determined), if any operand
is unsigned, the "result" is unsigned, regardless of the operator. If we
assume that this "result" is the resulting type that should be
propagated down the equality operands, then the resulting type should be
unsigned, since the left operand is unsigned. This is another weak part
of this reasoning.
*         Based on the above, the type propagated to the cast expression
from above is unsigned array of 4 elements, and the "initial" type of
the cast expression is signed array of 3 elements. The cast expression
should be extended, since 4 > 3. It should not be sign extended, since
the propagated type is unsigned. Therefore zero-extension should be used
(this is the case in Synopsys-DC).


Yossi