Re: [sv-bc] Is '1 > 1 ?

Steven Sharp thinks '1 > 1 is true and writes:
> ... without any special rules in the LRM, ['0, '1, 'X, and 'Z] must
> follow the existing rules.  If they are unsigned in a self-determined
> context, then they are unsigned.

This is the "self-determined type" that terms contribute to their
expression during Verilog's bottom-up phase of type balancing.
In SV, '{...} has its type imposed by an earlier top-down phase.

A lot of energy went into '{default:0} that might have been resolved
more succinctly by saying that '0 et al inherit their type from context,
and fill it with a monotone bitstream.  [It's an unsafe cast, but one
whose heavy-handedness models actual hardware...]

No proposal to that effect is hereby intended, but I wanted to be sure
that it hadn't crept in and been passed during the many meetings I was
absent ;-)

Greg