[sv-bc] Structure literal using data type

Hi,

   Is it the correct syntax to use structure literal?
   
    It seems to me vector or array type member assignment through 
structure literal is not clear in SV LRM.

Thanks
Subhankar

module test (input in1, input bit [15:0] in2, output reg [7:0] out1);

  typedef struct {
        bit a[4:0];
        logic [7:0] b;
} my_struct;

my_struct struct_obj1;

always @(in1 or in2)
  begin
    struct_obj1 = {logic [7:0] : in2, bit : in1};
    out1 = struct_obj1.b;
  end

endmodule