RE: [sv-bc] Naming of unnamed sequential blocks

Greg Jaxon
> Dave found a curious "loophole" though (excuse the pun).
> An unnamed scope breaks the access path (by fully qualified 
> names) to all entities nested in it at any depth.  This would 
> include paths to explicitly named blocks.  The scope 
> introduced by a local "for" index apparently cannot be named, 
> so acknowledging it means losing a standard name for the 
> entities it contains.  

The System Verilog 3.0 LRM said "The local variable declared 
within a for loop can be referenced hierarchically by adding a 
statement label before the for loop." This was taken out in later
versions because it was realized that the loop variable had to 
be automatic and you cannot have hierarchical references to 
automatic variables.

My understanding of this is that
 
for (int i=0; ...) begin end

is equivalent to

begin
   int i;
   for (i=0; ...) begin end
end

And

name: for (int i=0; ...) begin end

is equivalent to

begin : name
   int i;
   for (i=0; ...) begin end
end

This would allow a way to name the scope of loop index variables.

Mark Hartoog
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