[sv-bc] Small issue with array type rules

In 5.2 we have:
    SystemVerilog accepts a single number, as an alternative to a
    range, to specify the size of an unpacked array, like C. That
    is, [size] becomes the same as [0:size-1].

This doesn't specify whether it is an error if size <= 0.  I think
that was likely the intent, but since Verilog ranges can go in either
direction, [0:size-1] is valid for any value of size.  Does anyone
know whether non-positive values were intended to be allowed?  The
text above doesn't actually make it an error.

Gord.
-- 
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Gordon Vreugdenhil,  Staff Engineer               503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com