RE: [sv-bc] Proposal on striking the 2 paragraphs

Dave,

I do not claim it is possible to solve all the problems, but we should strive
to reduce them as much as possible. You must recognize that there is a 
difference between the ideal and reality. Besides, you have situations like
taking legacy code and modifying it, something we do all the time.

Shalom


On Sat, 16 Apr 2005, Rich, Dave wrote:

> Mark,
> 
> This is why I say no one should be using always @ anymore when using
> SystemVerilog. And as Steve pointed out, the implicit continuous
> assignment created when someone connects to a legacy Verilog block will
> create the necessary event that triggers the always block.
> 
> Dave
> 
> 
> > -----Original Message-----
> > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
> Mark
> > Hartoog
> > Sent: Saturday, April 16, 2005 2:30 PM
> > To: Shalom.Bresticker@freescale.com; 'Steven Sharp'
> > Cc: sv-bc@eda.org
> > Subject: RE: [sv-bc] Proposal on striking the 2 paragraphs
> > 
> > Another issue we have not discussed about initialization is constant
> > variables.
> > Consider:
> > 
> > logic x = 0;
> > const logic y = 1;
> > logic z;
> > 
> > always @(x) z = x & y;
> > 
> > If we start the always block before any of the initialization, and
> then we
> > execute the initialization of 'x', all LRMs allow a simulator to
> activate
> > the always block as soon as it sees the event for 'x' and before the
> > initialization of 'y'. If 'y' were not constant and was included on
> the
> > sensitivity list of the always block, this would not matter. When 'y'
> > got initialized later, the always block would be re-executed, and 'z'
> > would have the correct value.
> > 
> > Const variables do not belong on sensitivity list, and it seems silly
> to
> > require
> > them be put there anyway just so initialization works. Const variables
> > should,
> > in fact, be synthesizable, so this is not just a test bench issue.
> > 
> > It may be true that no real Verilog simulator would ever get the wrong
> > answer
> > for the above code, but this becomes much less clear when you start
> > talking
> > about const variables in packages.
> > 
> > Mark Hartoog
> > 700 E. Middlefield Road
> > Mountain View, CA 94043
> > 650 584-5404
> > markh@synopsys.com
> > 
> > 
> > 
> 

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