[sv-bc] Assignment pattern lvals (mantis 623)

I was asked to write up some of my concerns regarding
Mantis 623 (assignment pattern lvals).

Issue 1

What is the interpretation of somthing like:
    x = (U'{a,b} = expr);
In this context, I am assuming that the type of the LHS
of the inner assign is expected to be "U" and that the
*intermediate* object, initialized from expr is the
value of the assignment.

This should be clarified since one can't simply appeal
to {a,b} given the behavioral description of the
assignment operation.


Issue 2

Can assignment pattern expressions be actuals to
ref parameters or ref ports?  This is not specified
in the current text.


Issue 3

The current behavioral description implies that
net collapsing could not be done in input and output
net connections since there is an intermediate value
in play.  If one decides to describe the intermediate
as being a net type then one could run into situations
in which port connections become illegal since the
implied net would be a 2 state type.  The nature
of the implied intermediate (net or var) is fundamental
to the nature of the connection.  The simplest method
of resolving this would be to describe the the
intermediate as a var and then to describe both input
and output connections as a pair of continuous assigns.
Since the connection would propagate through a var,
this makes it clear the nets are not collapsed through
such a connection.  This is also the most restrictive
approach in terms of simulation efficiency,
propagation of forced values, etc.


Issue 4

The current behavioral description is completely inadequate
for inout port connections.  Since the behavioral
description has the implication of the "var" intermediate
as noted in Issue 4, the most consistent view would be
to disallow assignment patterns for inout ports in the
same manner in which vars are disallowed.


Issue 5

I am very uncomfortable with the propagation of type
information from the RHS to the LHS in expressions
such as:   '{a,b} = x
The only circumstance where right to left type
propagation current happens is when one has an
untyped parameter.  It isn't at all clear to me
what the impact of this will be when taken together
with other Verilog rules.


Given the lack of time to analyze this issue, I
wouldn't feel comfortable supporting this aspect
for the current LRM and think that we should require
typed assignment patterns in all lval contexts for
the current LRM.


Gord


-- 
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Gordon Vreugdenhil,  Staff Engineer               503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com