Hi all, As a user, I know we have "priority" used as a signal. But that doesn't bother me much because the users already gave up several of their favorite names such as bit, sequence etc... What bothers me most is that, priority is misleading. I didn't realize until now, that it is not what it means. Verilog already gives enough rope to kill the users. It seems like SystemVerilog is giving even more... Thanks, Uma > > >In my already stated opinion, the "priority" keyword sucks! But we are > >stuck with it. > > Note that "priority" is also one of the keywords most likely to appear > in legacy Verilog designs as an identifier, causing the design to fail > to compile under SystemVerilog. > > Steven Sharp > sharp@cadence.com > >Received on Tue Mar 29 11:48:00 2005
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