Re: [sv-bc] signing in the reign

From: Steven Sharp <sharp_at_.....>
Date: Thu Mar 03 2005 - 11:48:31 PST
>There isn't any good reason to stop there though: "signed logic S"
>should be a variable with the values -1 and 0.
>
>To a purist that's a valuable distinction.
>But I wonder if it has any practical appeal, especially
>since it messes with a C programmer's head?

I would take a different purist view, and say that there was a good
reason to stop before that point.  I would argue that the concept
of signedness does not apply to a scalar.  It can be applied to a
1-bit vector, but that is not the same thing.

The concept of signedness assumes that the object is a "number", an
ordered collection of bits with a value based on assigning each bit
a significance based on its index within that collection.  This
concept can be applied to a 1-bit vector as a degenerate case, since
that bit still has an index and a position within the vector.  However,
it cannot be applied to a scalar, since it has no index or position
within a collection.  A 1-bit vector is a collection of one element,
but a scalar is not a collection at all.  Note that the concept of
signedness ties directly into the concept of significance, since in
2s-complement, it can be viewed as simply changing the significance
of the leftmost bit from 2**N to -(2**N).

Now you may be accustomed to unconsciously regard a scalar much like
a 1-bit vector, and Verilog fosters that by converting a scalar into
a 1-bit vector in a vector expression, but technically they are not
the same.

If you want a vector of signed 1-bit numbers, you can still do this,
but only by declaring them as 1-bit signed vectors.


>Are you saying that P1800 is faced with resolving contradictory specs for
>this feature?

No.  I agree that associating signedness with distinct acts of aggregation
has theoretical appeal, and might have been a better language design.
However, it is not backward compatible with what was done in Superlog,
because it gives a different meaning for declarations that were legal
in Superlog.  The technical issues here do not appear to be strong enough
to overrule that, so the resolution has been made.


Steven Sharp
sharp@cadence.com
Received on Thu Mar 3 11:48:38 2005

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