Hi Greg; >There isn't any good reason to stop there though: "signed logic S" >should be a variable with the values -1 and 0. This would make Yes, for the degenerate case of 1 bit, this is true, but it does become confusing. E.g. some people do write: if (signed_bit == 1'b1) ... >signed logic [7:0] V; // and >logic signed [7:0] W; // different types. > V is an unsigned vector of signed bits > W is a signed vector of unsigned bits. >To a purist that's a valuable distinction. That may be true but very funny. if (V >= 4 || V[0] == -1'b1) -- THis seems definitely strange. Actually, doesn't bit and part selection remove the signed attribute? Is W[1:0] or V[1:0] signed? I haven't followed this. >But I wonder if it has any practical appeal, especially >since it messes with a C programmer's head? Good luck... -- Adam Krolnik ZSP Verification Mgr. LSI Logic Corp. Plano TX. 75074 Co-author "Assertion-Based Design"Received on Thu Mar 3 07:28:03 2005
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