RE: [sv-bc] issue with unions

From: Rich, Dave <Dave_Rich@mentorg.com>
Date: Tue Dec 07 2004 - 21:32:28 PST

Steven,

For what it's worth, I can give you some of the intent from my
historical perspective.

There should be nothing the user can do within SystemVerilog that would
generate a memory fault, other than running out of memory.

The original Superlog definition did not allow dynamically sized
elements in unpacked unions, but that restriction was removed in SV3.0
because the donation to Accellera did not include variable sized types.
When dynamically sized types were added back in SV3.1, they should have
put this restriction back.

Dave

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Steven Sharp
Sent: Tuesday, December 07, 2004 6:29 PM
To: sv-bc@eda.org
Subject: [sv-bc] issue with unions

I have filed a new issue 336, related to problematic types that are
apparently allowed in unions. Perhaps someone out there knows what
the intent was, or perhaps I have missed something in the LRM.

Steven Sharp
sharp@cadence.com
Received on Tue Dec 7 21:32:34 2004

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