Re: [sv-bc] Errata: variable initializers don't match Verilog-2001

I think there is a difference between compatibility between Verilog and
SystemVerilog and between Verilog and Verilog.

Shalom

On Sat, 4 Dec 2004, Steven Sharp wrote:

> Another point of view on this might be that, while this is not compatible
> with Verilog-2001, the benefits of greater determinacy are sufficient to
> justify making the change. But in that case, wouldn't the same argument
> apply to Verilog also? If this would be a good thing to change, then why
> wouldn't it be better to change it in Verilog-2005?
>
> Steven Sharp
> sharp@cadence.com
>

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Shalom Bresticker                        Shalom.Bresticker @freescale.com
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