RE: [sv-bc] Proposal for compatibility problems with mixed Verilog/SystemVerilog code

\Good \point

\-mac

-- On Nov 30 2004 at 17:39, Steven Sharp sent a message:
> To: stuart@sutherland-hdl.com, mac@verisity.com, sv-bc@eda.org
> Subject: "RE: [sv-bc] Proposal for compatibility problems with mixed Verilog/SystemVerilog code"
>
> >However the proposal needs more work. Three quick questions come to mind:
> >
> >Q1) How can one instantiate from an 1800 module a 1364 module that happens
> > to be named one of these newly reserved keywords?
> >
> >Q2) How could one instatiate by name a 1364-2005 module from a 1800-2005
> > parent module which names its arguments using what are now reserved
> > keywords?
> >
> >Q3) How could one make a cross module reference from a 1800-2005 module to
> > (or through) a 1364 module which uses a 1800 reserved word?
>
> I believe that all of these can be resolved by using Verilog escaped names.
> Not pretty, but it should work well enough for the rare situations where
> this occurs. It looks ugly in the following examples, but they are extreme.
>
>
> >`keywords 1800-2005
> >module p1800;
> >
> > logic [31:0] a,b,c;
> >
> > priority decoder1 ( .matches(a), .tagged(b), ,ignore_bins(c));
>
> \priority decoder1 ( .\matches (a), .\tagged (b), ,.\ignore_bins (c));
>
>
> > assign error = decoder.break;
>
> assign error = decoder.\break ;
>
> >
> >endmodule
> >`endkeywords
>
>
> Steven Sharp
> sharp@cadence.com
Received on Tue Nov 30 15:06:45 2004