RE: [sv-bc] Proposal for compatibility problems with mixed Verilog/SystemVerilog code

Love the idea; we do need this.

However the proposal needs more work. Three quick questions come to mind:

Q1) How can one instantiate from an 1800 module a 1364 module that happens
    to be named one of these newly reserved keywords?

Q2) How could one instatiate by name a 1364-2005 module from a 1800-2005
    parent module which names its arguments using what are now reserved
    keywords?

Q3) How could one make a cross module reference from a 1800-2005 module to
    (or through) a 1364 module which uses a 1800 reserved word?

EG:

`keywords 1800-2005
module p1800;

  logic [31:0] a,b,c;

  priority decoder1 ( .matches(a), .tagged(b), ,ignore_bins(c));
  
  assign error = decoder.break;

endmodule
`endkeywords

module priority(input [31:0] matches, ignore_bins, output [31:0] tagged);
 reg break;

 always @(foo) begin
   if (bad) break = 1;
 end
...
   
endmodule

-- On Nov 29 2004 at 18:06, Stuart Sutherland sent a message:
> To: sv-bc@eda.org
> Subject: "[sv-bc] Proposal for compatibility problems with mixed Verilog/SystemVerilog code"
> All,
>
> I have attached a complete proposal for the P1800 standard to fix a serious
> compatibility problem between the 1364 and 1800 standards. This
> compatibility is particularly a problem when mixing models from both
> standards, such as when a SystemVerilog module instantiates an IP model
> written in Verilog, or when a SystemVerilog netlist uses a Verilog standard
> cell library. At issue is the large number of keywords that SystemVerilog
> adds to Verilog. Many of these new reserved words were commonly used as net
> or variable identifiers in existing Verilog code (e.g.: as bit, byte and
> logic). Currently, software implementations must invent proprietary ways
> for a tool to read source code as either Verilog code or SystemVerilog code.
> Each tool I have used has invented different methods to handle the keyword
> differences in the two languages. Some tools do not handle mixing Verilog
> and SystemVerilog models at all. Keyword compatibility creates portability
> problems between software tools, and inhibits the adoption of SystemVerilog.
>
> The attached proposal provides a pair of compiler directives that make it
> simple to mix Verilog models and SystemVerilog models. By making these
> directives part of the SystemVerilog standard, user's can rely on a portable
> mechanism for using new SystemVerilog models together with their existing
> Verilog models.
>
> I would like to bring the attached proposal up for a vote in Tuesday's SV-BC
> meeting. Can someone please add this to the list of errata in the SV data
> base?
>
> Stu
>
> P.S. This compatibility problem was originally opened in the 1364 ETF data
> base, as item 287.
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland
> stuart@sutherland-hdl.com
> +1-503-692-0898
>
Received on Tue Nov 30 09:05:12 2004