Re: [sv-bc] Proposal for compatibility problems with mixedVerilog/SystemVerilog code

> b) Why do we need quotation marks? Why not just
>
> `keywords 1364-2005

The same reason that `include expects a string. It's just easier to
parse a string with arbitrary contents. What you have in your example
looks like integer literals on either side of a minus operator.

Paul
Received on Tue Nov 30 09:00:00 2004