Re: [sv-bc] SV_BC #26 - Enumerated Literals in Packages - Feedback Requested

From: Greg Jaxon <Greg.Jaxon@synopsys.com>
Date: Mon Nov 29 2004 - 10:30:52 PST

I don't see why the importation of an enumerated type also
needs to import its literal labels. They are separate names
and no one explicitly asked to have them imported.

On the contrary, when you used the wildcard import, you
explicitly renounced responsibility for what things matched
that wildcard, and so you got all names which the package
defines.

So I think your examples are generally backward.

module tmp1d;
import p::bool_t;
import q::teeth_t;

This is not an error! This module may create new objects of the
imported enum types and pass them off to (packaged) entities. The
types may be compared and queried.

module tmp2d;
import p::*;
import q::teeth_t; // OK
teeth_t myteeth;
   initial begin
   myteeth = FALSE; // ERROR, FALSE is a direct reference to p::bool_t::FALSE
                     // which was imported by the wildcard syntax.

module tmp3d;
import q::teeth_t;
typedef enum ( TRUE, FALSE ) story_t; //OK FALSE has no previous meaning.

Clifford E. Cummings wrote:
> Hi All -
>
> With respect to BUG ID #26 - I am inclined to propose that importing
> enumerated types with the same literal as existing or other imported
> enumerate types shall be an error, but importing with the wildcard
> package import is not necessarily an error. Examples attached.
>
> If all agree, I will write up the proposal and include the attached
> examples.
>
> Regards - Cliff
>
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
Received on Mon Nov 29 10:29:30 2004

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