RE: [sv-bc] SV-BC #110 - 2-State Divide by 0 question

Cliff,

I looked at this a while ago and found that there is no easy way to
define a 2-state division that is backward compatible with Verilog. For
example

integer A = 100 / 0;

Is this a 2-state division?

or what about

integer A;
int B;

A = A << B/0;

Are the above a 2 or 4-state divisions.

I think it may be useful to use context determination rules similar to
those used for width or signed determination.

'100/0' in the example above should return 1'bx because it is being used
in the context of a 4-state assignment.

'B/0' would be a 2-state division because it is a self-determined
expression.

I would like to use the same rules for determining the result of an out
of range array reference. Currently, the spec says to return the default
un-initialized value. I think designers would rather see it return 'x
when used in a 4-state context.

Dave

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Clifford E. Cummings
Sent: Tuesday, November 23, 2004 4:06 PM
To: sv-bc@eda.org
Subject: [sv-bc] SV-BC #110 - 2-State Divide by 0 question

Hi, All -

Don Mills and I have been asked to make a proposal for Issue #110 on
divide
by 0 in 2-state.

I believe Don and I will propose that divide by 0 in 2-state just gives
zero as a result. The problem is that the errata refers to a 1364
section
and I am not sure where we should add this in the SystemVerilog
standard.
There is no addition-operator related section in the SV standard to
amend
with this information.

Any suggestions?

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
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Received on Tue Nov 23 17:30:02 2004