Re: [sv-bc] const vs. constant in SV (Was: Data-Types: status of "var" proposal)

Dave,

I agree with you, but there are errors in the LRM about this issue
that may be responsible for much of the confusion. According to
Section 5.3 ("Constants"), a const variable is one of the three
kinds of constants. And it talks multiple times about 'constants'
that are 'declared with the const keyword'.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Rich,
Dave
Sent: Friday, November 19, 2004 3:17 PM
To: Greg Jaxon; Bradford Jonathan
Cc: btf-dtype@boyd.com; sv-bc@eda.org
Subject: RE: [sv-bc] const vs. constant in SV (Was: Data-Types: status
of "var" proposal)

Greg and Jonathan,

const and constant mean different things in SystemVerilog.

In Verilog and in SV, a constant are values that can be computed at
elaboration time. (Excuse me for not being more precise)

A const is a variable that is computed during the initialization phase
of the scope it is declared in. A static const will be initialized
before time 0, and an automatic const will be initialized when its block
is activated.

The main advantage of a static const variable over a parameter constant
is that it can be initialized with things like hierarchical references
to parameters, something that is not allowed in constant expressions.

Dave
Received on Fri Nov 19 17:36:11 2004