RE: [sv-bc] DataTypes: 11/18/04 Meeting Minutes

From: Kathy McKinley <mckinley@cadence.com>
Date: Thu Nov 18 2004 - 19:44:46 PST

Hi Mark,

Does your approval extend to the latest proposed changes for
the "var" keyword in a variable declaration?
 
Kathy

>From: "Mark Hartoog" <Mark.Hartoog@synopsys.com>
>To: "Kathy McKinley" <mckinley@cadence.com>
>Cc: <btf-dtype@boyd.com>, <sv-bc@eda.org>
>Subject: RE: [sv-bc] DataTypes: 11/18/04 Meeting Minutes
>Date: Thu, 18 Nov 2004 19:03:09 -0800
>
>I think the most recent versions of the data types on wires proposals look
>good to me.
>
>I think the typedef change to omit the type should not be part of the
>data types on wires proposal. If people want to pursue this, they can file
>a separate item for this.
>
>> -----Original Message-----
>> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Kathy
>> McKinley
>> Sent: Thursday, November 18, 2004 6:25 PM
>> To: Greg.Jaxon@synopsys.COM; mckinley@cadence.com
>> Cc: btf-dtype@boyd.com; sv-bc@eda.org
>> Subject: Re: [sv-bc] DataTypes: 11/18/04 Meeting Minutes
>>
>>
>> Hello Greg,
>>
>> Thank you for bringing this improper usage to our attention.
>> I have changed "comprised" to "composed".
>>
>> Kathy
>>
>> >Date: Thu, 18 Nov 2004 13:04:52 -0800
>> >From: Greg Jaxon <Greg.Jaxon@synopsys.com>
>> >Organization: //Synopsys/ICBU/HDL Compiler
>> >To: Kathy McKinley <mckinley@cadence.com>
>> >Cc: btf-dtype@boyd.com, sv-bc@eda.org
>> >Subject: Re: [sv-bc] DataTypes: 11/18/04 Meeting Minutes
>> >
>> >Kathy McKinley wrote:
>> >> Replace the paragraph in our proposal that begins
>> >> "The effect of this recursive definition is" with the following
>> >> two paragraphs:
>> >>
>> >> The effect of this recursive definition is that a net is comprised
>> >> entirely of four-state bits, and is treated accordingly. There is no change
>> >> to the Verilog-2005 network semantics. In addition to a signal value, each
>>> >> bit of a net shall have additional strength information. When bits of signals
>> >> combine, the strength and value of the resulting signal shall be determined
>> >> as in Verilog-2005 section 7.10.
>> >
>> >Just an english usage note:
>> >
>> > "is comprised entirely of" should probably say "is composed of".
>> >
>> > Wholes comprise their parts, and it is incorrect to use "comprise"
>> > and then leave out some of the parts - so saying "entirely" is redundant.
>> >
>> >Greg Jaxon
Received on Thu Nov 18 19:44:52 2004

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