Re: [sv-bc] The "var" keyword

Kevin,

> "reg" doesn't do what you say. In Verilog a reg declaration creates a
> behavioral driver for a net, if the net is not connected out of the
> module then it looks like a variable. The type of the driver is 4-state
> - which is the data-type "logic" in SV - the net can support the extend
> range of signal strengths so is not actually restricted to 4-state.

This may be the way you would like to look at it, but that is not what
the IEEE Std 1364 Verilog LRM says. You will not find there any statement
supporting that interpretation. Nor do implementations work that way.

Now it may be that different interpretations are equivalent in current
Verilog. But certainly, Kathy's is closer to the language of the LRM
and therefore simpler and more straightforward. So you can't claim that
your interpretation is right and hers is wrong.

Regards,
Shalom

-- 
Shalom Bresticker                        Shalom.Bresticker @freescale.com
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