This is a revised version of the changes for Section 18 for tomorrow.
Steven Sharp
sharp@cadence.com
Changes for Section 18 "Hierarchy"
In 18.1, CHANGE
"An important enhancement in SystemVerilog is the ability to pass any data
type through module ports, including nets, and all variable types including
reals, arrays and structures."
TO
"An important enhancement in SystemVerilog is the ability to pass a value
of any data type through module ports, using nets or variables. This
includes reals, arrays and structures."
In 18.8, CHANGE
"With SystemVerilog, a port can be a declaration of a net, an interface,
an event, or a variable of any type, including an array, a structure
or a union."
TO
"With SystemVerilog, a port can be a declaration of an interface, an event,
or a variable or net of any allowed type, including an array, a structure
or a union."
In 18.8, CHANGE
"If the first port direction but no type is specified, then the port type
shall default to wire. This default type can be changed using the
`default_nettype compiler directive, as in Verilog."
TO
"If the first port direction but no net type or data type is specified,
then the port shall default to a wire net type. This default net type
can be changed using the `default_nettype compiler directive, as in
Verilog."
In 18.8, CHANGE
"For subsequent ports in the port list, if the type and direction are
omitted, then both are inherited from the previous port. If only the
direction is omitted, then it is inherited from the previous port. If
only the type is omitted, it shall default to wire. This default type
can be changed using the `default_nettype compiler directive, as in
Verilog.
// second port inherits its direction and type from previous port
module mh3 (input byte a, b);
...
endmodule"
TO
"For subsequent ports in the port list, if the direction and the net and
data types are omitted, then the direction and any net and data types
are inherited from the previous port. If the direction is omitted,
but a net or data type is present, then the direction is inherited from
the previous port. If the direction is present, but the net and data
types are omitted, then the port shall default to a wire net type. This
default net type can be changed using the `default_nettype compiler
directive, as in Verilog.
// second port inherits its direction and data type from previous port
module mh3 (input byte a, b);
...
endmodule
For an inout port, if the net type is omitted, then the port shall
default to a wire net type. This default net type can be changed using
the `default_nettype compiler directive, as in Verilog.
// all four ports are inout with data type integer and net type wire
module mh2 (integer a, b, inout integer c, wire integer d);
...
endmodule"
In 18.11.3, DELETE
"- A port connection between a net type and a variable type of the same
bit length is a legitimate cast."
In 18.12, CHANGE
"SystemVerilog extends Verilog port connections by making all variable
data types available to pass through ports."
TO
"SystemVerilog extends Verilog port connections by making values of all
data types on variables and nets available to pass through ports."
In 18.12.2, CHANGE
"If a port declaration has a wire type (which is the default), or any
other net type,"
TO
"If a port declaration has a net type, such as wire,"
In 18.12.2, CHANGE
"- An output can be connected to a net type (or a concatenation of net
types) or a compatible variable type (or a concatenation of variable
types).
- An inout can be connected to a net type (or a concatenation of net
types) or left unconnected, but not to a variable type."
TO
"- An output can be connected to a net or variable (or a concatenation
of nets or variables) of a compatible data type.
- An inout can be connected to a net (or a concatenation of nets) of a
compatible data type, or left unconnected, but cannot be connected to a
variable."
In 18.12.4, CHANGE
"The same rules for assignment compatibility are used for compatible
port types for ports declared as an input or an output variable, or
for output ports connected to variables."
TO
"The same rules are used for compatible port types as for assignment
compatibility."
Received on Wed Nov 10 16:02:54 2004
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