Re: [sv-bc] Errata in SV 3.1a LRM Section 18.4: inconsistent use of error and warning

On Thu, Nov 04, 2004 at 09:12:20PM -0500, Steven Sharp wrote:
>
> >Adam says, however, in http://www.eda.org/sv-bc/hm/2047.html
> >that --
> >
> > "Requiring simulators to evaluate unique case branches and
> > issue errors may cause false errors to be reported due to
> > simulation evaluation artifacts and timed signal propagations."
> >
> >Does this mean that it is actually legal to violate the
> >uniqueness assertion, or just that a simulator could get confused
> >about whether the assertion was violated?
>
> I assume that he means that the simulator determines that the assertion
> is violated (without being confused), but that the user may not care
> about the violation except at certain times. For example, there might
> be a zero-width glitch into an illegal state and then back to a legal one.
> Say a one-hot encoding is changing state and it momentarily passes through
> a state with two bits hot. This might depend on event ordering that is
> considered nondeterministic.
>
> I don't see how a simulator can do anything about this. All it can do
> is test the condition when the case is evaluated, and report any violations.

Since unique and priority have implicit assertions associated with them,
should there be a mechanism to set further conditions on those assertions so
that there are no false warnings/errors?

For example:

unique @(posedge clk) case (sel)
  val1: etc...
endcase

or:

unique disable iff (~resetn) case (sel)
  val1: etc...
endcase

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-- Andrew MacCormack                            andrewm@cadence.com
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