RE: [sv-bc] E-mail Vote: Closes 12pm PST Nov 01

[Just thought I'd restate my view (from the AMS world).]

In AMS the general rule for handling nets with mixed drivers is that the
drivers are converted to drivers of the most accurate type of any driver
and resolved - this means inserting D-to-As that convert logic to
current/voltage and solving in a Spice-like manner. The resolved value
is converted back to logic through A-to-Ds if required.

For purposes of accurate modeling digital drivers are considered to be
continuous assigns, primitive outputs and regs - a reg being the
composite declaration of a wire and driver of type logic. Ports are not
considered drivers because they map to interconnect in hardware (not
active devices).

A net itself has no type in AMS, the type of a net is the resolved type
of the drivers of the net.

From an (A)MS perspective the logical extension of reg is to allow users
to type the reg declaration with something other than the default type
(logic) so that more views of what's on a wire can be supported. E.g. in
AMS there is a type "wreal" used for a single physical wire carrying a
real value (say voltage), so it would make sense to have:

      module foo (output voltage);

      reg wreal voltage;

      initial voltage = 1.0;

- which attaches driver of type real to the net voltage. Adding
resolution functions for a single type can be done the same way as it is
in VHDL (though resolution should be done flat). In SV I would expect
that other

types like "bool" could also be used e.g.:

      module bar (output on_or_of_and_no_maybe);

      reg bool on_or_of_and_no_maybe; // decisive driver

bool is a subtype of logic so it can be resolved with logic.

I would therefore suggest that "reg" as a synonym for "logic" is
deprecated ASAP.

If "reg" is used as a synonym for "logic" then you need to add new
syntax for declaring drivers which will need new keywords. However,
having said that you can dissociate the parts of a reg declaration and
gain some advantages e.g. something like:

      driver_decl ::= driver <type> <driver name> (<signal name>)

      driver bool decisive(on_or_off);

That lets you do multiple drivers for one signal in the same module.

Kev.

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Steven Sharp
Sent: Thursday, October 28, 2004 12:05 PM
To: sharp@cadence.com; Shalom.Bresticker@freescale.com
Cc: sv-bc@eda.org; matthew.r.maidment@intel.com
Subject: Re: [sv-bc] E-mail Vote: Closes 12pm PST Nov 01

>From: Shalom.Bresticker@freescale.com

>

>As a user, I don't have a problem with "parameter reg" or "function
reg".

>"wire reg" is a different story entirely.

The "datatypes on nets" group has decided to disallow the use of the
token

"reg" immediately following any nettype token. This was mostly to avoid

potential confusion or typos between "tri reg w" and "trireg w".
However,

it should also prevent anyone writing "wire reg w" in the belief that
this

will result in a wire that has more variable-like semantics. It was

decided to make this a lexical restriction on these specific tokens,
rather

than a semantic restriction that would treat the "reg" type differently

from the "logic" type. Presumably anyone going through a typedef will

understand better that they are using "reg" purely as a datatype.

Since this restriction is being done as a lexical rule, it doesn't

require a difference in semantic treatment of "reg" and "logic". As a

result, I am changing my vote on 163 from NO to ABSTAIN.

Steven Sharp

sharp@cadence.com

 
Received on Thu, 28 Oct 2004 13:01:33 -0700