As a user, I don't have a problem with "parameter reg" or "function reg".
"wire reg" is a different story entirely.
Shalom
On Wed, 27 Oct 2004, Steven Sharp wrote:
> I vote YES on everything except 163, where I vote NO.
>
> I don't believe it is desirable to have "reg" used interchangeably
> with "logic" as a datatype. I think "reg" should be treated as
> specifying a variable object kind, rather than a datatype. Even
> if it is treated as a datatype, I don't believe it is desirable to
> allow it to appear in all the places that "logic" can appear.
> Experienced Verilog users will find it jarring, and perhaps confusing,
> to allow declarations such as "parameter reg p = 0;" or
> "function reg f;" or worst of all "wire reg w;"
>
> Steven Sharp
> sharp@cadence.com
>
-- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential ProprietaryReceived on Wed Oct 27 21:11:09 2004
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