RE: [sv-bc] Built-in types are not packed arrays

V2K doesn't allow bit selects of its built-in integer types,
'integer' and 'time'. (Yes, most simulators support it anyway.)
So a V2K array of integers really does have just one dimension,
not two.

Also, $typename in SystemVerilog distinguishes built-in types.

Incidentally, I recommend against using the built-in integer
types in synthesis, except for things like for-loop iteration
variables, even though it will "work". As the V2K LRM says,
"An integer is a general-purpose variable used for manipulating
quantities that are not regarded as hardware registers."
If you really want a 32-bit signed hardware register, declare
its size explicitly.

-- Brad
Received on Fri Sep 24 12:12:52 2004