RE: [sv-bc] precedence of :/ vs. //

See for example C++, a language that defines such things in detail:
int a;
a = 4 /// hoho
2;
--> parse error before '2'
This means /// is parsed as // /, not as / //
so we have a line comment.
The C++ standard says:
"The next preprocessing token is the longest sequence ..."
There is no context awareness - it is purely done in the preprocessor
without regard of context.
I propose we have the same behavior in (System)Verilog.

However, if your tool has a Verilog2001 mode and a SystemVerilog mode,
the :// in your example would have to be preprocessed as
: // (2 tokens) for 2001, and as
:// (1 token) for SystemVerilog.

-Hermann

>
> SystemVerilog introduces the :/ operator. This creates a
> potential ambiguity when combined with comments. For instance:
>
> case (x)
> 2'b00:// this is a comment
>
> A naive lexer will see the ':' and the '/' characters next to
> each other and return the :/ operator. This will lead to a
> syntax error.
>
> Correct handing of the :/ operator requires some
> context-awareness in the lexer.
>
> Paul
>
Received on Wed Aug 25 07:03:10 2004