Re: [sv-bc] Partial proposal for issue #091- take #2

Hi,

As I wrote previously, in Verilog hierarchical references in parameter
overrides in module instance statements are allowed, whereas they are
not in parameter declarations and in defparams.

I don't know the reason.

Maybe it is a mistake to allow them in module instance statements
as well.

Shalom

On Mon, 23 Aug 2004, Guillermo Maturana wrote:

> If the intention of your footnote is to disallow hierarchical references
> infecting
> parameter overrides it may fall short. Parameter overrides must be
> elaboration
> time constants, which is more restrictive. You may end up with an xmr
> even if
> the expression looks OK, especially because of interfaces. Any parameter
> type
> override or default must be a constant expression, or for types, a
> constant type
> expression. I am not sure this is well defined, but excluding xmrs is
> definitely
> not enough. Again, interfaces are particularly problematic. You may use the
> "typeof" some interface's net to override a parameter type on some
> instance, but
> if that interface was passed to the module through an xmr in the high
> conn the
> simple test contained herein will not detect the case. Interfaces have
> the potential
> to cause as many elaboration problems as defparams if we are not careful.
>
> _Matute

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Shalom Bresticker                        Shalom.Bresticker @freescale.com
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