Hi Bhasker,
Your statement on SystemVerilog conflicting with Verilog
surprises me. We had the best known experts in the world that have
worked their entire career on Verilog (Phil Moorby, Peter Flake, and
many others within Cadence, Synopsys and Mentor) and many who have
developed working simulators and synthesis tools be part of the
committee for SystemVerilog. We also had several consultants that have
been working on Verilog standards since it started within IEEE (Stu,
Cliff to name a few)who helped to ensure high synergy between IEEE
Verilog and SystemVerilog. We are also using simulators from at least
two vendors and have not noticed such issues.
Anyhow, we are all human, and if we made a mistake, please let
us know ASAP. The best way is for you to send me an email directly if
you want and I will ensure that it is addressed. You can also join the
sv-bc reflector and send your errata directly to this committee. This
way you can also debate your points of views with the committee experts
on both Verilog and SystemVerilog.
If you want to add it yourself into the database let me and we
can set you with an account to directly input your Errata or concerns.
Please let us know.
Best Regards
Vassilios
-----Original Message-----
From: Brophy, Dennis [mailto:dennisb@model.com]
Sent: Friday, July 09, 2004 3:27 PM
To: 'stds-dasc-sc@eda.org'; 'Sv-bc@eda.org'; 'ieee1800@eda.org'
Cc: Gerousis Vassilios (CL DAT CS)
Subject: Re: DASC-SC: result of vote on 1364 PAR
Bhasker,
If you have issues with SystemVerilog I would suggest that you make your
specific issues known by entering errata on those issues you have.
Both the 1364 and SV teams have demonstrated a great deal of cross team
interaction the last few years. The presumption that that the parallel
activities have had or will have limited or no interaction is just plain
false.
Now that p1800 and p1364 are going to move under one working group it
seems hard for me to understand how this is a problem when it was not a
problem in the past. Is the DASC that broken?
Vassilios or David can provide you pointers to submit SystemVerilog
errata.
Regards,
Dennis
-- Dennis Brophy Email: dennisb@model.com Director of Strategic Business Development Phone: +1 503-685-0893 Mentor Graphics Corporation Fax: +1 503-685-0923 8005 Boeckman Rd, Bldg E-4 Mobile: +1 503-706-8987 Wilsonville, OR 97070-7777 Home Fax: +1 503-579-2664 -----Original Message----- From: owner-stds-dasc-sc@eda.org <owner-stds-dasc-sc@eda.org> To: stds-dasc-sc@eda.org <stds-dasc-sc@eda.org> Sent: Fri Jul 09 05:46:02 2004 Subject: RE: DASC-SC: result of vote on 1364 PAR I agree with Gabe on the steps that he has enumerated, especially on the paths where both P1800 and P1364 WGs continue their work in parallel for now. EXCEPT (1) cannot happen in isolation BECAUSE SystemVerilog designers did not built it cleanly on top of 1364 but added lower-level extensions that conflicts with 1364. So i suggest (1) with lower-level extensions that conflict with 1364 removed for now (standardize only the system level aspects of SystemVerilog). regards, - bhasker -----Original Message----- From: Gabe Moretti [mailto:gmoretti@comcast.net] Sent: Thursday, July 08, 2004 5:23 PM To: stds-dasc-sc@eda.org Subject: Re: DASC-SC: result of vote on 1364 PAR Although any action intended to move DASC toward the goal has to be praised, this particular action does not help me to understand what the final outcome is meant to be. I have not seen anywhere a clear statement of the goal of the DASC with respect to Verilog/SystemVerilog, nor have I seen a plan for what will happen after the PAR has been modified. I have seen some information regarding the desire to merge 1364 and 1800 into one WG, but this would go against the scope and purpose of P1800, since that WG is specifically designed to ballot the Accellera standard as an IEEE standard. So any work done by this particular WG pursuant the 1364 PAR would be out of scope. I would like to suggest the following: 1) decide what the goal is. Are we to have two standards or just one. The idea of two standards is not as far fetched as it may seem at first. I am sure that there will be a significant group of designers who will want to continue to use Verilog without the added overhead that SystemVerilog has. I also fully understand that users of SystemVerilog must be assured that Verilog is a proper subset of SystemVerilog. So, a family standard, one that includes both Verilog and SystemVerilog is not out of the question. I suppose one may argue for just one standard and allow partial implementations, like "synthesizable VHDL" in the early days of that language. We may want to look at how 802.11 has handled the various emanations in that standard family. 2) Having decided what we want to do, we should make a plan that details the actions to be taken, the dates by which the actions must be completed, and the dependencies those actions have with each other. 3) At this point we are ready to define the structure of the team responsible for implementation. Today I am not sure if there is one standards covered by two PARs or two standards covered by two PARs with one joint WG to insure harmonization. In the first case the new 1364 PAR may not be clear enough to pass NesCom, since item 3 says that the product of the work is a standard. Yet this standard will be hidden within another standard making the maintenance of the first standard quite problematic. In addition it would mean that the final document must have two standard numbers, something I am not quite sure the IEEE is ready to handle. I suppose that using colored inks we can separate one standard from the other in one document.:-)) If the goal is the latter, then it might be better to have two WGs, each one with its own goal, and to have a three person harmonization board that reviews and decides dependencies issues. Note that the second approach does not necessarily impact the schedule for approval set by P1800. Once the harmonization work is completed and the two documents brought into total conformance, the standard can be updated later, if required. In the mean time, users can use SystemVerilog all along, since a corrected Verilog 2001 is the base and any future work by 1364 WG will be harmonized with the 1800 WG. It just means that things will be moved around in the document to make it more readable. Since two WGs and two PARs generate two standards, it will then be necessary to modify the 1800 PAR to include the 1364 standard into the 1800 standard. This can be done easily and it should not cause much pain. My suggestion is to have just one standard for ease of maintenance and reference. To do so the DASC should consider the following sequential steps: 1) ballot P1800 as is as soon as possible and make it an IEEE standard. 2) harmonize the work of 1364 and 1800 toward the final document. 3) After the vote in item 1 modify the 1800 PAR to include the harmonized work of both 1364 and 1800. 4) Withdraw PAR1364. 5) From then on there is one PAR and one WG to manage the standard. 6) Ballot the new standard. Gabe ----- Original Message ----- From: "Peter Ashenden" <peter@ashenden.com.au> To: <stds-dasc-sc@eda.org> Sent: Monday, July 05, 2004 9:07 PM Subject: DASC-SC: result of vote on 1364 PAR Dear colleagues, Since we now have a 100% return of vote on the question of the 1364 PAR, The vote is now closed and the result is as follows: Affirmative: 9 Negative: 2 Abstain: 1 The motion is carried and the PAR is approved. Please see attached spreadsheet for details of voting positions and comments. I will forward the PAR (with corrections as noted in the comments) to NesCom for consideration in their next round of continuous processing. Regards, Peter Ashenden DASC Chair -- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106Received on Fri Jul 9 06:56:44 2004
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