[sv-bc] Issues

1) The V2k LRM defines constant functions, but there is nothing
in the System Verilog LRM to modify this. In light of the changes
changes in functions, I think some changes are required. For example,
output, inout and ref ports are probably not allowed on constant
functions called from constant expression, but could they be allowed
on functions called from other constant functions. What about dynamic
data types?

2) Chapter 22 on configurations and libraries is a little confusing.
The last sentence of 22.1 says "SystemVerilog adds support for interfaces
to Verilog configurations." Does this mean the programs can not be
configured?

Then Section 22.1 says "A library is a named collection of cells. A cell
is a module, macromodule, primitive, interface, program, package, or
configuration. A configuration is a specification of which source files
bind to each instance in the design." This talks about both programs and
packages. Is this suppose to imply that you can configure all those
kinds of cells? I hope you cannot configure packages.

Mark Hartoog
700 E. Middlefield Road
Mountain View, CA 94043
650 584-5404
markh@synopsys.com
Received on Thu May 20 08:39:07 2004