[sv-bc] RE: [sv-ac] SystemVerilog Errata Technical Planning Meeting on Ju ne 3 -- Mentor Graphics

Jay,

  There are no plans for a dial-in. The room is too large to accomdate it.

-Dennis

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Jay Lawrence
Sent: Monday, May 17, 2004 6:46 AM
To: Vassilios.Gerousis@Infineon.Com; sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
Subject: RE: [sv-ac] SystemVerilog Errata Technical Planning Meeting on June 3 -- Mentor Graphics

Vassilios or Dennis,

Will a dial-in be provided? I will be traveling to DAC the following week in San Diego and would prefer not to spend 2 weeks in California.

Jay

===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
> Vassilios.Gerousis@Infineon.Com
> Sent: Sunday, May 16, 2004 2:32 AM
> To: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
> Subject: [sv-ac] SystemVerilog Errata Technical Planning Meeting on
> June 3 -- Mentor Graphics
> Importance: High
>
>
> Dear DV Committee members,
> Mentor Graphics, will host our meeting planned for June 3. The room
> is limited in size, so first come, first reserved. All SV chairs have
> seating. People who responded on my earlier email, have also a place.
>
> Date: June 3, 2004.
> Place: Mentor Graphics
> http://mentorgraphics.com/corp_info/map_sv.html
> 1001 Ridder Park Dr.
> San Jose, CA 95131
> Time: 9:30 AM -- 1:00 PM
> Topic: SystemVerilog 3.1A Errata, Process, and Support for IEEE
> working Group
> Phone: No teleconference number will be provided.
>
> Agenda
> =======
> 1- Introduction and organizational discussions
> 2- Accellera SystemVerilog 3.1A Standard:
> a- Errata List and status from each SV committee
> sv-ac,
> sv-bc,
> sv-ec,
> sv-cc
> b- Feedback from members on the final LRM.
> c- Modeling Library Status: The use of these models for compliance of
> Accellera Standard.
> 3- Errata plans, process, release schedule, etc.
> a- Errata versus enhancement.
> b- Maintaining Compatibility: Backward compatibility with
> SystemVerilog 3.1A and 1364 2001 release. Continued cooperation
> with IEEE 2001 Errata Committee.
> c- Planned Errata Release Manuals on a regular basis.
> d- Proposed process for errata submission, discussion, and approval.
> e- Others
> 4- Technical Support plans for IEEE standardization of SystemVerilog:
> Examples are
> a- Plans for handing the LRM to IEEE.
> b- Support on Errata List for IEEE.
> c- Interface to IEEE working group.
> d- Interpretation and technical support.
> e- Help in IEEE LRM version development.
> 5- Summary
>
> Best Regards
>
> Vassilios
>
>
> SystemVerilog Committee Meeting Invitation Email Dated May First 2004
> =====================================================
> Dear SystemVerilog Committee members,
> SystemVerilog 3.1A standard will require continual efforts on our
> parts to support Errata based on tool implementation and usage. We
> have done this for 3.1 and we will continue doing this for 3.1A. In
> addition, we will provide interpretation and help for the IEEE
> committee that will standardize 3.1A. Many of us has spent the last
> three years developing and enhancing SystemVerilog. We believe this
> standard is strong and stable to stand on its feet and go through IEEE
> process based on it completeness.
> Our plan is to form a working group out of the four ones we have and
> focus on Errata and interpretation. Part of this activity is to also
> cooperate with IEEE committee who will standardize SystemVerilog. We
> will release Errata document on a regular schedule based on EDA
> implementation feedback and also on usage feedback.
> The first meeting of this errata committee is planned for June 3rd.
> It will be in San Jose. It will start at 9:30 AM and spend at least
> four hours in the organization and definition. We will also define the
> process of how to work with an IEEE working group that will
> standardize SystemVerilog. An Agenda and detail will be released soon.
>
> Best Regards
>
> Vassilios Gerousis
>
>
Received on Mon May 17 10:20:43 2004