[sv-bc] Erratta - Change to casting rules

This is a small but significant change to the casting rules. The intent
of this change is to ensure that an implicit cast, if so defined,
behaves identically to it explicit casting form.

This is to say that if

typeA A = expr; // is valid statement,
typeA A = typeA'(expr); // is also an a valid statement with identical
results

The two changes needed to accomplish this are (and these are changes to
text added late in the SV3.1a process)

1. the expression to be cast is context determined instead of
self-determined
2. unpacked array assignments need to have type equivalence instead of
just assignment compatibility of their elements

For more background, see these earlier e-mail threads
http://www.eda.org/sv-bc/hm/1672.html
http://www.eda.org/sv-bc/hm/1682.html

-- 
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David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625