Re: Errata - RE : [sv-bc] A question about type casting

From: Dave Rich <David.Rich@synopsys.com>
Date: Thu Mar 25 2004 - 12:43:17 PST

The way the spec current reads, wire is not a data type, it is a net.
They are from different kingdoms. Data has the concept of storage class
like static and automatic. Nets don't contain data, they represent the
resolution of the drivers connected to them (Even a trireg net is not a
register, it is a capacitive driver attached to the net).

When copying one unpacked array to another, we want to be able to do
this without interpreting the contents of each element (among other
reasons). We can do this for unpacked array data types by enforcing type
equivalence rules.

We did, however, define assignment compatibility between wires and
variables in SV-BC-61a See
http://www.eda.org/sv-bc/hm/att-0665/01-03-17-03_minutes.htm This is
allowed for wires because they have to go through a resolution or
driving operation, instead of a data copy.

The current LRM says only the unpacked dimensions should be the same,
but I think this should be changed as part of this errata to make
implicit/explicit casting rules match.

Dave

Maidment, Matthew R wrote:

>I'm no fan of loaded answers, but I'll bite.
>
>So how are the datatypes of
>
> wire [2:0] wiremda [1:0];
> logic [2:0] logicmda [1:0];
>
>different?
>
>Matt
>
>
>
>>-----Original Message-----
>>From: Steven Sharp [mailto:sharp@cadence.com]
>>Sent: Wednesday, March 24, 2004 5:31 PM
>>To: Jacobi, Dan; sv-bc@eda.org; Maidment, Matthew R
>>Subject: RE: Errata - RE : [sv-bc] A question about type casting
>>
>>
>>
>>
>>>In summary, it is most useful that these:
>>>
>>> wire [2:0] wiremda [1:0];
>>>logic [2:0] logicmda [1:0];
>>>
>>>are assignment compatible in one easy step:
>>>
>>> assign logicmda = wiremda;
>>> assign wiremda = logicmda;
>>>
>>>I'd prefer that type equivalence be used very carefully
>>>in this section or ensure that a provision for the above
>>>is maintained.
>>>
>>>
>>If you could declare nets of the same datatypes as variables,
>>then this would be possible, regardless of the type compatibility
>>requirements.
>>
>>Steven Sharp
>>sharp@cadence.com
>>
>>
>>
>>
>
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625
Received on Thu Mar 25 12:43:24 2004

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