[sv-bc] A question about type casting

Hello All,

Section 4.7 in the LRM (Draft 5) "Array assignment" reads:

"Assigning to a fixed-size unpacked array requires that the source and
the target both be arrays with the same

number of unpacked dimensions, and the length of each dimension be the
same. Assignment is done by assigning

each element of the source array to the corresponding element of the
target array, which requires that the

source and target arrays be of compatible types. Compatible types are
types that are assignment compatible.

Assigning fixed-size unpacked arrays of unequal >>>size<<< to one
another shall result in a type check error.

...

An array of wires can be assigned to an array of variables having the
same number of unpacked dimensions

and the same length for each of those dimensions, and vice-versa."

Note the use of the word size

Section 4.8 adds the following Example

"task fun(int a[3:1][3:1]);

declares task fun that takes one argument, a two dimensional array with
each dimension of size three. A call to

fun must pass a two dimensional array and with the same dimension size 3
for all the dimensions. For example,

given the above description for fun, consider the following actuals:

...

reg b[3:1][3:1]; // OK: assignment compatible type"

Meaning that for the following RTL

                typedef logic [0:0] src_type [1:0];

typedef logic [1:0] trg_type [1:0];

src_type src;

trg_type trg;

always_comb trg = src; // legal implicit cast ?

There is an implicit type cast between src_type and trg_type

Meaning that the always_comb process is equivalent to

always_comb begin

            trg[0] = {1'b0, src[0]};

            trg[1] = {1'b0, src[1]};

end

Section 3.16 "Bit-stream casting" reads:

"If both source_t and dest_t are fixed sized unpacked types of different
>>>sizes<<< then a cast generates a compile-

time error."

Assuming that the phrase "different sizes" means different number of
bits then the explicit cast between the same two types should issue a
compile time error,

Or in other words the following RTL is illegal

typedef logic [0:0] src_type [1:0];

typedef logic [1:0] trg_type [1:0];

src_type src;

trg_type trg;

always_comb trg = trg_type'(src); // illegal cast ?

Now for my questions

1. Does the term different sizes in section refer to the number of
bits meaning the size of both src_type is 2 bits and the size of
trg_type is 4 bits, or does the word size refer the number of unpacked
element / words meaning the size of both src_type and trg_type is 2
elements. (Do we need any clarification)
2. Assuming the answer to my first quest is size == number of bits
- should we use the word size in section 4.7 and 4.16 in a different
way.
3. Again assuming the same answer to the first question - does this
mean that the implicit type casting between src_type and trg_typr is
legal, but the xplicit cast between the same two types is not ?

Thanks

Dan Jacobi,

Intel Corporation

Tel : +(972)-4-8655855

 
Received on Wed Mar 17 11:09:26 2004