[sv-bc] Fixes for some SV-BC open errata

Below are fixes for 4 minor SV-BC open errata.

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As pointed out in --

     http://www.eda.org/sv-bc/display_issue.cgi?issue_num=151

in 7.14 at the top of p. 72, REPLACE

     s = ""

WITH

     s : ""

-----------------

As pointed out in --

     http://www.eda.org/sv-bc/display_issue.cgi?issue_num=152

in 7.14, in the example at the bottom of p. 71 and top
of p. 72, in the typedef at the bottom of p. 72, REPLACE

      bit [31:0] c;

WITH

      bit signed [31:0] c;

and in the assignment at the top of p. 72, REPLACE

      bit [31:0]:1

WITH
      int:1

-----------------

As pointed out in --

     http://www.eda.org/sv-bc/display_issue.cgi?issue_num=160

in 11.25 in the title of the section, REPLACE

     ",structures, and unions"

WITH
     "and structures"

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The fix (LRM-169) for the following was incomplete --

    http://www.eda.org/sv-bc/display_issue.cgi?issue_num=166

In the examples of 2.7, REMOVE the comment

    "// 3 integers packed together"

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Received on Thu Mar 11 14:50:53 2004